Research Computer Scientist, Reconfigurable Computer Architecture

USC's Information Sciences Institute (ISI), a unit of the university's Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications, and artificial intelligence technologies. ISI's faculty, professional staff, and graduate students conduct extraordinary information sciences research at locations in Arlington, Virginia; Marina del Rey, California; and Waltham, Massachusetts.

ISI's Computational Systems and Technology Division is seeking a Research Computer Scientist to lead research and development in reconfigurable computer architectures. The position will focus on programmable compute and control structures that can rapidly switch among signal-processing, communications, and related workloads while meeting demanding throughput, latency, power, and resource constraints. The scientist will develop architectural concepts, models, and prototypes; guide implementation and evaluation across hardware and software; and work with interdisciplinary teams to mature architectures for sponsored research and transition. Initial applications may include adaptive communications and coding, a multifunction RF system on chip, or related efforts, depending on awards and program direction.

The Reconfigurable Computing Group turns ambitious computing ideas into working hardware. Its researchers connect architecture, algorithms, and implementation, taking designs from early concepts through FPGA demonstrations and custom silicon development. The group also develops tools that make these systems programmable and verifiable, including AI-assisted methods for hardware design, testing, device characterization, and debugging.

This position is based in ISI's Arlington, Virginia office.

Architecture and research

Define and evolve reconfigurable architectural components, including processing elements, configurable compute fabrics, control and scheduling mechanisms, on-chip communication, memory and data movement, and interfaces to external systems. Formulate research questions and conduct trade studies involving rapid reconfiguration, determinism, throughput, energy efficiency, scalability, and programmability. Develop performance models and publishable technical results.

Prototype and evaluation

Lead architecture modeling, RTL and FPGA prototyping, integration, verification, and benchmarking in collaboration with hardware, compiler, software, and application researchers. Investigate AI-assisted and agent-based methods for HDL design, testbench generation, and design exploration, and verify generated artifacts against functional and performance requirements. Establish representative workloads and measurable requirements, analyze bottlenecks, and guide design changes. Support application demonstrations such as adaptive encoding and decoding workflows or multifunction RF signal processing, as program needs warrant.

Technical leadership and sponsored research

Provide technical direction to researchers, engineers, and students; coordinate architecture deliverables across collaborating organizations; document designs and results for sponsors; contribute to proposals, reports, publications, and presentations; and engage prospective transition partners regarding architecture requirements and evaluation.

Minimum Qualifications

• Doctorate in computer engineering, electrical engineering, computer science, or a closely related field.
• Demonstrated research contributions in computer architecture or reconfigurable computing.
• Ability to reason across architecture and implementation, with experience in performance modeling, simulation, RTL design, FPGA prototyping, or related hardware development.
• Proficiency in Python or C++ for architecture modeling and evaluation, and working knowledge of Verilog, VHDL, or SystemVerilog for digital hardware prototypes.
• Strong technical writing, collaboration, and research leadership skills.
• Ability to handle Controlled Unclassified Information (CUI). Per U.S. government regulations, eligibility to handle CUI requires U.S. citizenship or permanent residency.

• Five or more years of relevant research experience.
• Expertise in coarse-grained reconfigurable arrays, heterogeneous or domain-specific accelerators, RISC-V or Arm processors, high-bandwidth interconnects, high-speed I/O, or hardware-software co-design.
• Experience with RF or DSP workloads, error-control coding, communication systems, ASIC development, verification, compiler or runtime integration, or sponsor-funded research.
• Familiarity with FPGA and ASIC implementation and verification tools, such as Vivado, Verilator, or commercial EDA flows.
• Experience applying AI coding assistants or agents to Verilog, VHDL, or SystemVerilog development, verification, or hardware design exploration.

The annual base salary range for this position is $140,000 to $180,000. When extending an offer of employment, the University of Southern California considers factors such as, but not limited to, the scope and responsibilities of the position, the candidate's work experience, education and training, key skills, internal peer equity, federal, state, and local laws, contractual stipulations, grant funding, and external market and organizational considerations.

• Work on exciting and engaging projects with real-world impact.
• Contribute across the full project lifecycle in a small-team environment.
• Enjoy a workplace that supports a quality work-life balance.
• Access opportunities for top-tier university education for you and your children.
• Receive comprehensive benefits, from medical coverage to matched retirement contributions.